ISO/IEC INTERNATIONAL STANDARD 15205 IEEE Std 1496 First edition 2000-06 SBus - Chip and module interconnect bus IEC Reference number ISO/IEC 15205:2000(E) so IEEE Std 1496,1993 Edition Copyright International Organization for Standardization ted without license from IHS Not for Resale Abstract: An input/output expansion bus with a 32- or 64-bit width is described in this standard. The SBus is designed for systems requiring a small number expansion ports. SBus Cards may be connected to a standard Sbus Connector mounted on the motherboard. SBus Devices may also be attached to the SBus directly on the system's motherboard. The dimensions of the SBus Card are 83,8 mm by 146,7 mm, making the cards appropriate for small computer systems that make extensive use of highly integrated circuits. The SBus Cards are designed to be installed in a plane parallel to the system's motherboard as mezzanine cards. They are designed to provide connections for devices external to the computer system through an exposed back panel. The form factor is useful in Futurebus+, VMEbus, desktop computers, and similar applications. The SBus has the capability of transferring data at rates up to SBus Cards may either serve as Masters on the bus, providing all virtual address information as well as the data to be transferred, or they may serve as Slaves on the bus, providing data transfer according to the requirements of some other SBus Master. The SBus Master for a data transfer is selected by an arbitration process managed by the single SBus Controller on the SBus. The SBus Controller provides a virtual to physical address translation service. Keywords: I/O bus, SBus, SBus Card, Standard for Boot Firmware. The Institute of Electrical and Electronics Engineers, Inc. 345East47thStreet,NewYork,NY10017-2394,USA Copyright @ 1993 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. First published in 1993. ISBN 2-8318-5165-3 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without thepriorwrittenpermissionofthepublisher. CapyrghtIntematinal organization for Standardization Not for Resale ISO/IEC INTERNATIONAL STANDARD 15205 IEEE Std 1496 First edition 2000-06 SBus - Chip and module interconnect bus Sponsor Bus Architecture Standards Committee ofthelIEEEComputerSociety IEC PRICECODE XA S C For price,see currentcatalogue Copyright International Organization for Standardization ted without license from IHS Not for Resale ISO/IEC 15205:2000(E) 2 IEEE Std 1496,1993Edition CONTENTS Page FOREWORD INTRODUCTION Clause General.. 8 1.1 Scope and object.. 1.2 Normative references.. 2 Definitions, usage of special terms, acronyms, and editorial conventions .. 2.1 Definitions. 2.2 Usage of special terms . 13 2.3 Acronyms. 13 2.4 Editorial conventions.. 13 3 Overview.. 14 3.1 System overview.. 3.2 Overview of configurations.... 16 3.3 General design information... 19 3.4 Performance 21 4 Signal definitions 23 4.1 CLK signal ... ..23 4.2 RST* signal 24 4.3 PA[27:0] signals.. .25 4.4 SEL* signal. 25 4.5 As* signal. 26 4.6 BR* signal... 26 4.7 BG* signal . 4.8 D[31:0], D[63:0], and DP signals 27 4.9 SIZ[2:0] signals, 4.10 RD signal. .28 4.11 ACK[2:0]* signals. 29 4.12 LERR* signal. .31 4.13 INT[7:1]* signals . .32 5 SBus cycle definitions 33 5.1 Arbitration Phase. 5.2 Translation Phase. .34 5.3 Extended Transfer Information Phase .36 5.4 Transfer Phase . 40 5.5 Dual function SBus Devices 58 5.6 Exception conditions 59 5.7 Extended Transfer locking protocol .60 Copyright @ 1993 IEEE. All rights reserved. Copyright International Organization for Standardization ted without license from IHS Not for Resale ISO/IEC 15205:2000(E) - 3 - IEEEStd1496,1993Edition Clause Page 6 SBus electrical requirements. .62 6.1 Power. .62 6.2 Electronic characteristics. 6.3 Electronic timing requirements... 6.4 Compliance requirements, ..69 7 Environmental requirements. 7.1 Operating range.. .69 8 Mechanical require